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Data Sheet
ADuM3220/ADuM3221
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ V DD1 ≤ 5.5 V, 4.5 V ≤ V DD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over T J = ?40°C to +125°C. All typical specifications are at T J = 25°C, V DD1 = 5 V, V DD2 = 10 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
Output Supply Current, Two Channels, Quiescent
I DDI(Q)
I DDO(Q)
1.2
4.7
1.5
10
mA
mA
Total Supply Current, Two Channels 1
DC to 1 MHz
V DD1 Supply Current
V DD2 Supply Current
I DD1(Q)
I DD2(Q)
1.4
11
1.7
17
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
Input Currents
I IA , I IB
?10
+0.01
+10
μA
0 V ≤ V IA , V IB ≤ V DD1
Logic High Input Threshold
Logic Low Input Threshold
V IH
V IL
0.7 × V DD1
0.3 × V DD1
V
V
Logic High Output Voltages
V OAH , V OBH
V DD2 ? 0.1
V DD2
V
I Ox = ?20 mA, V Ix = V IxH
Logic Low Output Voltages
V OAL , V OBL
0.0
0.15
V
I Ox = +20 mA, V Ix = V IxL
Undervoltage Lockout, V DD2 Supply
Positive-Going Threshold
V DD2UV+
4.1
4.4
V
Negative-Going Threshold
Hysteresis
V DD2UV?
V DD2UVH
3.2
3.7
0.4
V
V
Positive-Going Threshold
V DD2UV+
7.0
7.5
V
Negative-Going Threshold
Hysteresis
V DD2UV?
V DD2UVH
6.0
6.5
0.5
V
V
Output Short-Circuit Pulsed Current 2
I OA(SC) , I OB(SC)
2.0
4.0
A
V DD2 = 10 V
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
R OA , R OB
R OA , R OB
0.3
0.3
1.3
0.9
3.0
3.0
?
?
V DD2 = 10 V
V DD2 = 10 V
SWITCHING SPECIFICATIONS
Pulse Width 3
Data Rate 4
PW
50
1
ns
MHz
C L = 2 nF, V DD2 = 10 V
C L = 2 nF, V DD2 = 10 V
Propagation Delay 5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
t DLH , t DHL
t DLH , t DHL
t PSK
t PSKCD
t PSKCD
t R /t F
t R /t F
I DDI(D)
I DDO(D)
35
36
14
14
45
50
1
1
20
22
0.05
1.5
60
68
12
5
7
25
28
ns
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
V DD2 = 10 V
V DD2 = 10 V
Refresh Rate
f r
1.2
Mbps
1
2
3
4
5
6
7
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Short-circuit duration less than 1 μs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
t DLH propagation delay is measured from the time of the input rising logic high threshold, V IH , to the output rising 10% threshold of the V Ox signal. t DHL propagation
delay is measured from the input falling logic low threshold, V IL , to the output falling 90% threshold of the V Ox signal. See Figure 20 for waveforms of propagation
delay parameters.
t PSK is the magnitude of the worst-case difference in t DLH and/or t DHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Rev. C | Page 3 of 16
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